The present invention generally relates to computer technology, and more specifically, to tracking ownership updates across multiple simultaneous operations in a processor.
Modern computer packaging technology provides for a modular design that may be used in a variety of computer system products in conjunction with a computer memory. In one example, multiple processor cores may be packaged on a single module or chip die. In another example, multiple chip cores may be packaged with storage control function on a single module or chip die. The multiple processor cores employ a cache hierarchy on the module or chip die. Further, only a single core of the module or chip die may be used in a computer system. In one example, only a single such module or chip die may be used in a computer system. Alternatively, multiple such modules or chip dies may be used in a computer system. Each configuration above may require a different cache coherency protocol to efficiently perform desired function and performance.